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Application Note 9611
Inductances which are in series with each power MOSFET
also control di/dt. Stray inductance between the filter capacitor
and the positive and negative bus rails help reduce the
switching di/dt.
In the eval-board, no inductance is added to control the di/dt.
A small parasitic inductance exists naturally in the printed
circuit board and component layout. Secondary-side inverter
gate-to-source capacitors control the di/dt commutation rate.
Additionally, a snubber (R 38 -C 27 ) was employed across the
inverter output terminals to control switching transients. The
gate-source capacitors help reduce the ringing at the
inverter bridge terminals associated with the output choke
employed to reduce EMI.
Bootstrap Supply Design
The bootstrap supply technique is a simple, cost-effective
way to power the upper MOSFET’s gate and provide bias
supply to the floating logic sections of the HIP4082. Only two
components per bridge phase are needed to implement the
bootstrap supply. For a full bridge driver such as the
HIP4082, diodes D 1 and D 2 , and capacitors C 1 and C 2 are
all that is needed to provide this function as shown in the
schematic in the Appendix.
The bootstrap capacitor gets charged or “refreshed” using
the low voltage (V CC ) bias supply. A fast recovery diode is
connected between the bootstrap capacitor and V CC , with
the anode going to V CC and the cathode to the capacitor.
The other side of the capacitor is tied to COM or V SS
potential through a low-side power MOSFET throughout the
period during which the low-side MOSFET or its body diode
is conductive. Since the body diode conduction depends on
some remaining load current at the time that an upper
MOSFET is turned off, it is generally wise to reserve a short
period during every PWM cycle to turn on the lower
MOSFET, thereby guaranteeing that refresh occurs.
The refresh time allotted must last long enough to replace all
of the charge that is sucked out of the bootstrap capacitor
during the time since the last refresh period ended. There
are 3 components of charge which must be replaced. The
least significant is that due to the bias supply needs of the
upper logic section of the HIP4082, which typically will be
145 μ A when the MOSFET is gated on and about 1.5mA
when it is gated off. Bootstrap diode leakage current will
normally be negligible, but should be investigated. The
required charge is the upper bias supply current of the
HIP4082 integrated over one PWM period.
The second component, usually very significant, is the charge
required to pump up the equivalent MOSFET input
capacitance to the V CC level. The charge, Q GATE , is equal to
the product of the equivalent gate capacitance, C GATE , and
the magnitude of gate voltage applied, V CC . The power
dissipated in pumping this charge is the product of the charge,
Q GATE , the applied voltage, V CC , and the frequency of
application, f PWM . Most MOSFET data sheets supply values
3
for Q GATE at 10V and at 20V. Obtain the equivalent C GATE by
taking the charge given in the data sheet for 10V and dividing
it by 10. Multiply the equivalent C GATE by the actual operating
V CC to get the actual Q GATE .
The third component of charge lost during each switching
cycle is that due to the recovery of the bootstrap diode. This
charge component is insignificant if one uses a fast or ultra-
fast recovery bootstrap diode. Ultra-fast recovery diodes are
recommended (see the Bill of Material included in the
Appendix).
The upper bias supply operating current will vary with PWM
duty-cycle. The upper bias current is typically 1.1mA when
driving a 1000pF load with a 50kHz switching voltage
waveform (at a 50% duty-cycle). This value represents the
sum of all three of the previously discussed components of
current. Figure 14 of the HIP4082 datasheet [1] shows typical
full bridge level-shift current as a function of switching
frequency (at a 50% duty-cycle). As duty-cycle decreases, the
level-shift current increases somewhat. The best way to
determine the exact level of current is to measure it at the
duty-cycle desired. In many applications, the duty-cycle is
constantly changing with time. Therefore a 50% duty-cycle
waveform is a good choice for purposes of determining
bootstrap average current requirements.
The level-shift current also tends to increase with frequency,
because the leading edge of each level-shift signal
incorporates a robust current pulse to guarantee that the
translation pulse is not interrupted by stray IC currents
induced by the high dv/dt levels which occur during
switching. Figure 14 of the HIP4082 data sheet includes this
effect also.
Special Concerns
When the HIP4082 IC first powers up, there is a 400ns to
500ns pulse applied to both lower MOSFET gates which
serves to charge the bootstrap capacitors for the first time.
This action corresponds with a simultaneous off pulse to
both upper MOSFETs through the level-shift circuitry. If it is
necessary to completely charge the bootstrap capacitors
upon power-up, then this pulse imposes limitations on the
size allowed for the bootstrap capacitors. If too large, they
may not get charged within the 400ns to 500ns window. The
start-up pulses are sent regardless of what state the input
logic signals (except for DIS) are in at the time.
In the event that MOSFETs are used with very large Gate-
Source input capacitances (or when several smaller
MOSFETs are paralleled) complete charging of the
bootstrap capacitors can be guaranteed by issuing lower
MOSFET turn-on pulses of a longer duration than the default
duration issued by the HIP4082. The peak current drawn
from the V CC supply can be quite severe in the case of a
1.0 μ F bootstrap capacitor, for example. In this example, it
would take 24A to charge the capacitor in 0.5 μ s. Obviously
the bootstrap diode equivalent series resistance, coupled
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